Cumulative Balance Testing of Logic Circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 3, Issue 1, 1995, Pages 72-83

  Chakrabarty, Krishnendu ^a   Hayes, John P ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0002588372     PISSN: 10638210     EISSN: 15579999     Source Type: Journal    
DOI: 10.1109/92.365455     Document Type: Article

References (24)

1. S. B. Akers, “A parity bit signature for exhaustive testing,” IEEE Trans. Comput.-Aided Design, vol. 7, pp. 333-338, Mar. 1988.
2. M. Abramovici, M. A. Breuer, and A. D. Friedman. Digital Systems Testing and Testable Design. New York: Computer Science Press, 1990.
3. B. Bose, “Group-theoretic signature analysis,” IEEE Trans. Comput., vol. 39, pp. 1398-1403, Nov. 1990.
4. F. Brglez and H. Fujiwara, “A neutral netlist of 10 combinational benchmark circuits and a target simulator in Fortran,” in Proc. IEEE Int. Symp. Circuits, Syst., 1985, pp. 695-698.
5. K. Chakrabarty and J. P. Hayes, “Balance testing of logic circuits,” in.Proc. IEEE Int. Symp. Fault-Tolerant Computing, 1993, pp. 350-359.
6. K. Chakrabarty and J. P. Hayes, “DFBT: A design for testability method based on balance testing,” in Proc. Design Automat. Conf., 1994, pp. 351-357.
7. K. Chakrabarty and J. P. Hayes, “Efficient test response compression for multiple-output circuits,” in Proc. IEEE Int. Test Conf., 1994, pp. 501-510.
8. R. David, “Comments on ' ‘Signature analysis for multiple output circuits’,” IEEE Trans. Comput., vol. 39, pp. 287-288, Feb. 1990.
9. W. Feller, An Introduction to Probability Theory and its Applications, 3rd ed., vol. 1. New York: Wiley, 1967.
10. H. K. Lee and D. S. Ha, “An efficient forward fault simulation algorithm based on the parallel pattern single fault propagation,” in Proc. IEEE Int. Test Conf., 1991, pp. 946-955.
11. E. J. McCluskey, “Verification testing—A pseudoexhaustive test technique,” IEEE Trans. Comput., vol. 33, pp. 541-546, June 1984.
12. E. J. McCluskey and S. Bozorgui-Nesbat, “Design for autonomous test,” IEEE Trans. Comput., vol. 30, pp. 866-875, Nov. 1981.
13. D. K. Pradhan and S. K. Gupta, “A new framework for designing and analyzing BIST techniques and zero aliasing compression,” IEEE Trans. Comput., vol. 40, pp. 743-763, June 1991.
14. S. Pilarski and K. J. Wiebe, “Counter-based compaction: An analysis for BIST,” J. Electron. Testing: Theory, Applicat., vol. 3, pp. 33-43, 1992.
15. I. Pomeranz, L. N. Reddy, and S. M. Reddy, “COMPACTEST: A method to generate compact test sets for combinational circuits,” in Proc. IEEE Int. Test Conf., 1991, pp. 194-203.
16. J. E. Smith, “Measures of effectiveness of fault signature analysis,” IEEE Trans. Comput., vol. 29, pp. 510-514, June 1980.
17. R. Srinivasan, S. K. Gupta, and M. A. Breuer, “An efficient partitioning strategy for pseudo-exhaustive testing,” in Proc. Design Automat. Conf., 1993, pp. 242-248.
18. J. Rajski and J. Tyszer, “Test response compression in accumulators with rotate-carry adders,” IEEE Trans. Comput.-Aided Design, vol. 12, pp. 531-539, Apr. 1993.
19. N. R. Saxena and J. P. Robinson, “Accumulator compression testing" IEEE Trans. Comput., vol. 35, pp. 317-321, Apr. 1986.
20. Texas Instruments, The TTL Data Book, Dallas, TX, 1988.
21. T. W. Williams, W. Daehn, M. Gruetzner, and C. W. Starke, “Aliasing errors in signature analysis registers" IEEE Design, Test Comput., vol. 4, pp. 39-45, Apr. 1987.
22. D. Xavier, R. C. Aitken, A. Ivanov, and V. K. Agarwal, “Using an asymmetric error model to study aliasing in signature analysis registers,” IEEE Trans. Comput.-Aided Design, vol. 11, pp. 16-25, Jan. 1992.
23. Y. You and J. P. Hayes, “Implementation of VLSI self-testing by regularization,” IEEE Trans. Comput.-Aided Design, vol. 7, pp. 1261-1271, Dec. 1988.
24. Y. Zorian and A. Ivanov, “Programmable space compaction for BIST,” in Proc. IEEE Int. Symp. Fault-Tolerant Computing, 1993, pp. 340-349.