PQE2000: HPC tools for industrial applications

IEEE Concurrency

Volumn 6, Issue 4, 1998, Pages 68-73

  Vanneschi, Marco ^a,b  

^a UNIVERSITY OF PISA   (Italy)

^b Pisa Parallel Processing Centre   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0002474079     PISSN: 10923063     EISSN: None     Source Type: Journal    
DOI: 10.1109/4434.736429     Document Type: Article

References (11)

1. M. Vanneschi, "Heterogeneous HPC Environments," Lecture Notes in Computer Science, Vol. 1470, Springer-Verlag, Berlin, pp. 21-34.
2. B. Bacci et al., SkIE User Manual, tech. report, QSW, Pisa, Dec. 1997.
3. 3L: A Structured Parallel Programming Language and Its Structured Support," Concurrency: Practice and Experience, Vol. 7, No. 3, May 1995, pp. 225-255.
4. M. Vanneschi, "Variable Grain Architectures for MPP Computation and Structured Parallel Programming," Proc. Third Int'l Working Conf. Massively Parallel Programming Models, IEEE Computer Society Press, Los Alamitos, Calif., 1998.
5. S. Pelagatti, Structured Development of Parallel Programs, Taylor & Francis, London, 1997.
6. S. Pelagatti, "Compiling and Supporting Skeletons on MPP," Proc. Third Int'l Working Conf. Massively Parallel Programming Models, IEEE CS Press, 1998.
7. S. Orlando and R. Perego, COLT-HPF, A Coordination Layer for HPF Tasks, Tech. Report TR CS-98-4, Dept. of Mathematics and Computer Science, Univ. of Venice, 1998.
8. T. Sterling, P. Messina, and P.H. Smith, Enabling Technologies for Peta(FL)OPS Computing, CCSF-45, Caltech Concurrent Supercomputing Facilities, California Inst. of Technology, Pasadena, Calif., 1994.
9. K. Likharev, "Advanced Technologies for PetaFlops Computing," Proc. Advanced Research Workshop on High Performance Computing, 1998.
10. P.M. Kogge, "EXECUBE - A New Architecture for Scalable MPPs," Proc. Int'l Conf. Parallel Processing, 1994, pp. 177-184.
11. P.M. Kogge et al., "Combined DRAM and Logic for Massively Parallel Systems," Proc. Conf. Advanced Research VLSI, 1995, pp. 4-16.