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Volumn 1, Issue 1, 1990, Pages 73-87

Design considerations for Parallel pseudoRandom Pattern Generators

Author keywords

[No Author keywords available]

Indexed keywords


EID: 0002279899     PISSN: 09238174     EISSN: 15730727     Source Type: Journal    
DOI: 10.1007/BF00134016     Document Type: Article
Times cited : (27)

References (16)
  • 1
    • 84935144777 scopus 로고    scopus 로고
    • B. Koenemann, J. Mucha, and G. Zwiehoff, “Built-in logic block observation techniques,” Proc. 1979 Test Conf., Cherry Hill, NJ, October, pp. 37–41.
  • 2
    • 84935121879 scopus 로고    scopus 로고
    • P.H. Bardell and W.H. McAnney, “Self-testing of multi-chip logic modules,” Digest of Papers, 1982 IEEE Test Conf., Philadelphia, November 15–18, pp. 200–204.
  • 5
    • 84935058116 scopus 로고    scopus 로고
    • P.H. Bardell, W.H. McAnney, and J. Savir, op. cit. Built-in Test for VLSI, Wiley, New York, 1987, p. 81.
  • 7
    • 84935088147 scopus 로고    scopus 로고
    • D. Tang and C.L. Chen, “Logic test pattern generation using linear codes,” Proc. 13th Fault Tolerant Computing Symposium (FTCS-13), Milano, June 28–30, 1983, pp. 222–226.
  • 11
    • 84935071465 scopus 로고    scopus 로고
    • P.H. Bardell, W.H. McAnney, and J. Savir, op. cit. Built-in Test for VLSI, Wiley, New York, 1987, p. 87.
  • 12
    • 84935104699 scopus 로고    scopus 로고
    • L.T. Wang and E.J. McCluskey, “A hybrid design of maximum-length sequence generators,” Proc. IEEE Intern. Test Conf., pp. 38–45, Washington, D.C., September 1986.
  • 14
    • 84935140789 scopus 로고    scopus 로고
    • P.H. Bardell, W.H. McAnney, and J. Savir, op. cit. Built-in Test for VLSI, Wiley, New York, 1987, p. 155.
  • 15
    • 84935067020 scopus 로고    scopus 로고
    • Op. cit. p. 171.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.