-
3
-
-
0000568889
-
Minimization over boolean graphs
-
Apr.
-
J. P. Roth and R. M. Karp, "Minimization Over Boolean Graphs," IBM Journal, pp. 227-238, Apr. 1962.
-
(1962)
IBM Journal
, pp. 227-238
-
-
Roth, J.P.1
Karp, R.M.2
-
4
-
-
0003089216
-
Technology mapping via transformations of function graphs
-
Oct.
-
S. Chang and M. Marek-Sadowska, "Technology Mapping via Transformations of Function Graphs," in Proc. Int'l Conf. Computer Design, pp. 159-162, Oct. 1992.
-
(1992)
Proc. Int'L Conf. Computer Design
, pp. 159-162
-
-
Chang, S.1
Marek-Sadowska, M.2
-
5
-
-
0027271156
-
Bdd based decomposition of logic functions with application to fpga synthesis
-
June
-
Y.-T. Lai, M. Pedram, and S. Vrudhula, "BDD Based Decomposition of Logic Functions with Application to FPGA Synthesis," in Proc. Design Automation Conf., pp. 642-647, June 1993.
-
(1993)
Proc. Design Automation Conf.
, pp. 642-647
-
-
Lai, Y.-T.1
Pedram, M.2
Vrudhula, S.3
-
6
-
-
0002553248
-
Fpga design by generalized functional decomposition
-
Kluwer Academic Publishers, (T. Sasao, ed.)
-
T. Sasao, "FPGA Design by Generalized Functional Decomposition," in Logic Synthesis and Optimization (T. Sasao, ed.), pp. 233-258, Kluwer Academic Publishers, 1993.
-
(1993)
Logic Synthesis and Optimization
, pp. 233-258
-
-
Sasao, T.1
-
7
-
-
0022769976
-
Graph-based algorithms for boolean function manipulation
-
Aug.
-
R. E. Bryant, "Graph-Based Algorithms for Boolean Function Manipulation," IEEE Trans. Computers, vol. C-35, pp. 667-691, Aug. 1986.
-
(1986)
IEEE Trans. Computers
, vol.C-35
, pp. 667-691
-
-
Bryant, R.E.1
-
8
-
-
0030644910
-
Restricted simple disjunctive decompositions based on grouping symmetric variables
-
Mar.
-
H. Sawada, S. Yamashita, and A. Nagoya, "Restricted Simple Disjunctive Decompositions Based on Grouping Symmetric Variables," in Proc. the Seventh Great Lakes Symposium on VLSI, pp. 39-44, Mar. 1997.
-
(1997)
Proc the Seventh Great Lakes Symposium on VLSI
, pp. 39-44
-
-
Sawada, H.1
Yamashita, S.2
Nagoya, A.3
-
9
-
-
0027841575
-
Detection of symmetry of boolean functions represented by robdds
-
Nov.
-
D. Moller, J. Mohnke, and M. Weber, "Detection of Symmetry of Boolean Functions Represented by ROBDDs," in Proc. Int'l Conf. Computer-Aided Design, pp. 680-684, Nov. 1993.
-
(1993)
Proc. Int'L Conf. Computer-Aided Design
, pp. 680-684
-
-
Moller, D.1
Mohnke, J.2
Weber, M.3
-
10
-
-
0018038632
-
A digital synthesis procedure under function symmetries and mapping methods
-
Nov.
-
C. R. Edwards and S. L. Hurst, "A Digital Synthesis Procedure Under Function Symmetries and Mapping Methods," IEEE Trans. Computers, vol. c-27, pp. 985-997, Nov. 1978.
-
(1978)
IEEE Trans. Computers
, vol.C-27
, pp. 985-997
-
-
Edwards, C.R.1
Hurst, S.L.2
-
11
-
-
0025531771
-
Shared binary decision diagram with attributed edges for efficient boolean function manipulation
-
jun
-
S. Minato, N. Ishiura, and S. Yajima, "Shared Binary Decision Diagram with Attributed Edges for Efficient Boolean Function Manipulation," in Proc. Design Automation Conf., pp. 52-57, jun 1990.
-
(1990)
Proc. Design Automation Conf.
, pp. 52-57
-
-
Minato, S.1
Ishiura, N.2
Yajima, S.3
-
12
-
-
0028455029
-
On area/depth trade-off in lutbased fpga technology mapping
-
June
-
J. Cong and Y. Ding, "On Area/Depth Trade-Off in LUTBased FPGA Technology Mapping," IEEE Trans. on VLSI systems, vol. 2, pp. 137-148, June 1994.
-
(1994)
IEEE Trans. on VLSI Systems
, vol.2
, pp. 137-148
-
-
Cong, J.1
Ding, Y.2
-
13
-
-
0003934798
-
Sis: A system for sequential circuit synthesis
-
Univ. of California, Berkeley, may
-
E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. Sangiovanni- Vincentelli, "SIS: A System for Sequential Circuit Synthesis," Memorandum UCB/ERL M92/41, Univ. of California, Berkeley, may 1992.
-
(1992)
Memorandum UCB/ERL M92/41
-
-
Sentovich, E.M.1
Singh, K.J.2
Lavagno, L.3
Moon, C.4
Murgai, R.5
Saldanha, A.6
Savoj, H.7
Stephan, P.R.8
Brayton, R.K.9
Sangiovanni-Vincentelli, A.10
-
14
-
-
33748603660
-
Logic synthesis and optimization benchmarks user guide version 3.0
-
Jan.
-
S. Yang, Logic Synthesis and Optimization Benchmarks User Guide Version 3.0. MCNC, Jan. 1991.
-
(1991)
MCNC
-
-
Yang, S.1
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