Tolerating latency through software-controlled prefetching in shared-memory multiprocessors

Journal of Parallel and Distributed Computing

Volumn 12, Issue 2, 1991, Pages 87-106

  Mowry, Todd ^a   Gupta, Anoop ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0002031606     PISSN: 07437315     EISSN: None     Source Type: Journal    
DOI: 10.1016/0743-7315(91)90014-Z     Document Type: Article

References (26)

1. Weak ordering—A new definition
2. April: A processor architecture for multiprocessing
3. Cache coherence protocols: Evaluation using a multiprocessor simulation model
4. Synchronization, coherence, and event ordering in multiprocessors
5. Evaluating the performance of four snooping cache coherency protocols
6. Performance evaluation of memory consistency models for shared-memory multiprocessors
7. Memory consistency and event ordering in scalable shared-memory multiprocessors
8. Tango introduction and tutorial
9. Compiler-directed data prefetching in multiprocessors with memory hierarchies
10. MASA A multithreaded processor architecture for parallel symbolic computing
11. Lockup-free instruction fetch/prefetch cache organization
12. Data prefetching in shared memory multiprocessors
13. Multiprocessor cache design considerations
14. The effectiveness of caches and data prefetch buffers in largescale shared memory multiprocessors
15. Design of scalable shared-memory multiprocessors: The DASH approach
16. The directory-based cache coherence protocol for the DASH multiprocessor
17. Vectorization of a particle simulation method for hypersonic ratified flow
18. Software methods for improvement of cache performance on supercomputer applications
19. Concurrent miss resolution in multiprocessor caches
20. Cache memories
21. Parallel distributed-time logic simulation
22. Measurement, analysis, and improvement of the cache behavior of shared data in cache coherent multiprocessors
23. Exploring the benefits of multiple hardware contexts in a multiprocessor architecture: Preliminary results