Data flow based cache prediction using local simulation

Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

Volumn 2000-January, Issue , 2000, Pages 155-160

  Wolf, F ^a   Ernst, R ^a  

^a TECHNICAL UNIVERSITY OF BRAUNSCHWEIG   (Germany)

Author keywords

Analytical models; Computational modeling; Computer architecture; Data analysis; Electrical equipment industry; Performance analysis; Predictive models; Software performance; Testing; Timing

Indexed keywords

ANALYTICAL MODELS; COMPUTER ARCHITECTURE; COMPUTER TESTING; DATA REDUCTION; DATA TRANSFER; MICROPROCESSOR CHIPS; REGRESSION ANALYSIS; SOFTWARE TESTING; TESTING;

COMPUTATIONAL MODEL; ELECTRICAL EQUIPMENT; PERFORMANCE ANALYSIS; PREDICTIVE MODELS; SOFTWARE PERFORMANCE; TIMING;

DATA FLOW ANALYSIS;

EID: 0001673257     PISSN: 15526674     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HLDVT.2000.889577     Document Type: Conference Paper

References (15)

1. A. Agarwal. Analysis of Cache Performance for Operating Systems and Multiprogramming. Kluwer Academic Publishers, 1989.
2. A. V. Aho, R. Sethi, and J. Ullman. Compilers: Principles, Techniques and Tools. Addison-Wesley, Reading, GB, 1988.
3. C. Ferdinand and R. Wilhelm. On predicting data cache behavior for real-time systems. In Proceedings of Language, Compilers and Tools for Embedded Systems, 1998.
4. J. Gonzalez. Static cache prediction based on data flow analysis for cache lines. Master's thesis, Technical University of Braunschweig, Germany, 2000.
5. C. Healy, R. Arnold, F. Mueller, D. Whalley, and M. Harmon. Bounding pipeline and instruction cache performance. IEEE Transactions on Computers, pages 53-70, Jan. 1999.
6. J. L. Hennessy and D. A. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kaufmann Pub., 1996.
7. A. Hergenhan and W. Rosenstiel. Static timing analysis of embedded software on advanced processor architectures. In Proceedings of Design, Automation and Test in Europe (DATE '00), pages 552-559, Paris, March 2000.
8. M. Hill. DINERO Cache Simulator: Code, Documentation. http://www.ece.cmu.edu/ece548/tools/dinero/src/, 1998.
9. S.-K. Kim, S. Min, and R. Ha. Efficient worst case timing analysis of data caching. In Proceedings of the IEEE Real-Time Technology and Applications Symposium, 1996.
10. Y. Li, S. Malik, and A. Wolfe. Performance estimation of embedded software with instruction cache modeling. ACM Transactions on Design Automation of Electronic Systems, 4(3):257-279, July 1999.
11. Y.-T. S. Li and S. Malik. Performance Analysis of Real-Time Embedded Software. Kluwer Academic Publishers, 1999.
12. R. Morgan. Building an Optimizing Compiler. Butterworth-Heinemann, 1998.
13. F. Wolf and R. Ernst. Software timing and power estimation of telecom systems. ESPRIT MEDIA Published Report, Technical University of Braunschweig, Germany, 1999.
14. F. Wolf and R. Ernst. Intervals in software execution cost analysis. In Proceeding of the IEEE International Symposium on System Synthesis, Madrid, Spain, 2000.
15. W. Ye and R. Ernst. Embedded program timing analysis based on path clustering and architecture classification. In Proceedings of ICCAD, pages 598-604, San Jose, 1997.