A design for FPGA implementation of the probabilistic neural network

ICONIP 1999, 6th International Conference on Neural Information Processing - Proceedings

Volumn 2, Issue , 1999, Pages 556-559

  Minchin, Graham ^a   Zaknich, Anthony ^a  

^a UNIVERSITY OF WESTERN AUSTRALIA   (Australia)

Author keywords

[No Author keywords available]

Indexed keywords

BINS; INTEGRATED CIRCUIT DESIGN; NEURAL NETWORKS;

CITY-BLOCK DISTANCES; CLASSIFIER PERFORMANCE; FPGA IMPLEMENTATIONS; HARDWARE DESIGN; PRACTICAL PROBLEMS; PROBABILISTIC NEURAL NETWORKS; SPHERICAL BASIS; VECTOR COMPONENTS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 0001483844     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICONIP.1999.845654     Document Type: Conference Paper

References (3)

1. Specht, D. F., "Probabilistic neural networks", International Neural Network Society, Neural Networks, Vol 3, 1990, pp. 109-118.
2. Specht, D. F., "Probabilistic neural networks and the polynomial ADALrNE as complementary techniques for classification", IEEE Transactions on Neural Networks, Vol. 1, No 1, March 1990, pp. 111-121.
3. Zaknich, A., "A vector quantisation reduction method for the probabilistic neural network, IEEE Proceedings of the International Conference on Neural Networks (ICNN), Vol II, Houston, Texas, USA, 9-12th June, 1997, pp. 1117-1120.