An optimal clock period selection method based on slack minimization criteria

ACM Transactions on Design Automation of Electronic Systems

Volumn 1, Issue 3, 1996, Pages 352-370

  Chang, En Shou ^a   Gajski, Daniel D ^a   Narayan, Sanjiv ^b,c  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b Viewlogic Systems Inc

^c Viewlogic Systems Inc   (United States)

Author keywords

Clock period; Clock slack; Performance estimation; Scheduling 1996 acm

Indexed keywords

EID: 0001307041     PISSN: 10844309     EISSN: None     Source Type: Journal    
DOI: 10.1145/234860.234864     Document Type: Article

References (17)

1. BALAKRISHNAN, M. AND MARWEDEL, P. 1989. A synthesis approach for design space exploration. In Proceedings of the Design Automation Conference (Las Vegas, NV), 68-74.
2. GAJSKI, D. 1996. Principles of Digital Design. Prentice Hall, NJ.
3. GAJSKI, D., DUTT, N., WU, C., AND LIN, Y. 1991. High-Level Synthesis: Introduction to Chip and System Design. Kluwer Academic, Boston, MA.
4. GAJSKI, D., VAHID, F., NARAYAN, S., AND GONG, J. 1994. Specification and Design of Embedded Systems. Prentice Hall, Englewood Cliffs, NJ.
5. JAIN, R., MLINAR, M., AND PARKER, A. 1988. Area-time model for synthesis of nonpipelined designs. In Proceedings of the International Conference on Computer-Aided Design (Santa Clara, CA).
6. KLM, T., LIU, J., AND LIU, C. 1991. A scheduling algorithm for conditional resource sharing. In Proceedings of the International Conference on Computer-Aided Design (Santa, Clara, CA).
7. RUNG, S., WHITEHOUSE, H., AND KAILATH, T. 1985. VLSI and Modern Signal Processing. Prentice-Hall, Englewood Cliffs, NJ.
8. MCFARLAND, M. AND KOWALSKI, T. 1990. Incorporating bottom-up design into hardware synthesis. IEEE Trans. Comput.-Aided Des. 9, 9 (Sept.).
9. PANG, D. AND FERRARI, L. 1989. Unified approach to general IFIR filter design using the B-spline function. In Proceedings of the Asilomar Conference on Signals, Systems & Computers.
10. PARK, N. AND PARKER, A. 1985. Synthesis of optimal clocking schemes. In Proceedings of the Design Automation Conference (Las Vegas, NV).
11. PARKER, A., PIZZARO, T., AND MLINAR, M. 1986. MAHA: A program for datapath synthesis. In Proceedings of the Design Automation Conference (Las Vegas, NV).
12. PAULIN, P. AND KNIGHT, J. 1989. Algorithms for high-level synthesis. In IEEE Des. Test Comput. (Dec.).
13. PAULIN, P., KNIGHT, J., AND GIRZYC, E. 1986. HAL: A multi-paradigm approach to datapath synthesis. In Proceedings of the Design Automation Conference.
14. RAMACHANDRAN, L. AND GAJSKI, D. 1994. Behavioral design assistant (bda) user's manual. UC Irvine, Dept. of ICS, Tech. Rep. 94-36.
15. VLSI TECHNOLOGIES INC. 1988. VDP100 1.5 Micron CMOS Datapath Cell Library.
16. VLSI TECHNOLOGIES INC. 1992. 0.8-Micron Datapath Library (VCC4DP3).
17. WALKER, R. AND CAMPOSANO, R. 1991. A Survey of High-Level Synthesis Systems. Kluwer Academic, Boston, MA.