Bipolar Transistor Modeling of Avalanche Generation for Computer Circuit Simulation

IEEE Transactions on Electron Devices

Volumn 22, Issue 6, 1975, Pages 334-338

  Dutton, Robert W ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0001190370     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1975.18132     Document Type: Article

References (11)

1. P. L. Hower and V. G. K. Reddi, “Avalanche injection and second breakdown in transistors,” IEEE Trans. Electron Devices, vol. ED-17, pp. 320-335, Apr. 1970.
2. R. A. Kokosa and R. L. Davies, Avalanche breakdown of diffused silicon p-n junctions,” IEEE Trans. Electron Devices, vol. ED-13, pp. 874-881, Dec. 1966.
3. C. D. Bulucea and D. C. Prisecaru, “The calculation of the avalanche multiplication factor in silicon p-n junctions taking into account the carrier generation (thermal or optical) in the space-charge region,” IEEE Trans. Electron Devices, vol. ED-20, pp. 692-701, Aug. 1973.
4. J. L. Moll, J. L. Su, and A. C. M. Wang, “Multiplication in collector junctions of silicon n-p-n and p-n-p transistors,” IEEE Trans. Electron Devices, vol. ED-17, pp. 420-423, May 1970.
5. H. C. Poon and J. C. Meckwood, “Modeling of avalanche effect in integral charge control model,” IEEE Trans. Electron Devices, vol. ED-19, pp. 90-97, Jan. 1972.
6. J. G. Fossum, “A bipolar device modeling technique applicable to computer-aided circuit analysis and design,” IEEE Trans. Electron Devices, vol. ED-20, pp. 582-593, June 1973.
7. S. L. Miller, “Ionization rates for holes and electrons in silicon,” Phys. Rev., vol. 105, pp. 1246-1249, Feb. 15, 1957.
8. T. E. Idleman, F. S. Jenkins, W. J. McCalla, and D. O. Pederson, “SLIC—A simulator for linear integrated circuits,” IEEE J. Solid-State Circuits, vol. SC-6, pp. 188-203, Aug. 1971.
9. R. D. Thornton, D. DeWitt, E. R. Chenette, and P. E. Gray, Characteristics and Limitations of Transistors. New York: Wiley, 1966, p. 45.
10. I. A. Cermak and D. B. Kirby, “Nonlinear circuits and statistical design,” Bell Syst. Tech. J., vol. 50, no. 4, pp. 1173-1198, Apr. 1971.
11. W. J. McCalla and W. G. Howard, Jr., “Bias-3—A program for the nonlinear dc analysis of bipolar transistor circuits,” IEEE J. Solid-State Circuits, vol. SC-6, pp. 14-19, Feb. 1971.