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Volumn 3, Issue 2, 1995, Pages 273-291

Critical Paths in Circuits with Level-Sensitive Latches

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Indexed keywords


EID: 0000981228     PISSN: 10638210     EISSN: 15579999     Source Type: Journal    
DOI: 10.1109/92.386227     Document Type: Article
Times cited : (22)

References (19)
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    • checkTcand min Tc: Timing verification and optimal clocking of synchronous digital circuits
    • Nov.
    • K. A. Sakallah, T. N. Mudge, and O. A. Olukotun, “check Tc and min Tc: Timing verification and optimal clocking of synchronous digital circuits,” in ICCAD-90 Digest of Technical Papers, pp. 552-555, Nov. 1990.
    • (1990) ICCAD-90 Digest of Technical Papers , pp. 552-555
    • Sakallah, K.A.1    Mudge, T.N.2    Olukotun, O.A.3
  • 3
    • 84941871746 scopus 로고
    • A pseudo-polynomial algorithm for verification of clocking schemes
    • Timing Iss., Spec., Synth. Digit. Syst., Mar. 18-20
    • N. Shenoy, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, “A pseudo-polynomial algorithm for verification of clocking schemes,” in TAU ' ‘92: Proc. 1992 ACM/SIGDA Workshop, Timing Iss., Spec., Synth. Digit. Syst., Mar. 18-20, 1992.
    • (1992) TAU ' ‘92: Proc. 1992 ACM/SIGDA Workshop
    • Shenoy, N.1    Brayton, R.K.2    Sangiovanni-Vincentelli, A.L.3
  • 5
    • 0026961616 scopus 로고
    • Computing optimal clock schedules
    • T. G. Szymanski, “Computing optimal clock schedules,” in Proc. Des. Automa. Conf., pp. 399-404, 1992.
    • (1992) Proc. Des. Automa. Conf. , pp. 399-404
    • Szymanski, T.G.1
  • 10
    • 0019896149 scopus 로고
    • x2018;Timing analysis of computer hardware
    • Jan.
    • R. B. Hitchcock, Sr., G. L. Smith, and D. D. Cheng, ' ‘Timing analysis of computer hardware,” IBM J. Res. Develop., vol. 26, no. 1, pp. 100-105, Jan. 1982.
    • (1982) IBM J. Res. Develop. , vol.26 , Issue.1 , pp. 100-105
    • Hitchcock, R.B.1    Smith, G.L.2    Cheng, D.D.3
  • 11
    • 0002284147 scopus 로고
    • The fastest algorithm for the PERT problem with AND-and OR-nodes (the new product-new technology problem)
    • Univ. Waterloo, Math. Programm. Soc., Waterloo, Ont., Canada, Univ. Waterloo Press, May 28-30
    • E. A. Dinic, “The fastest algorithm for the PERT problem with AND-and OR-nodes (the new product-new technology problem),” in Integer Programming and Combinatorial Optimization: Proc. Conf., Univ. Waterloo, Math. Programm. Soc., Waterloo, Ont., Canada, Univ. Waterloo Press, May 28-30, 1990.
    • (1990) Integer Programming and Combinatorial Optimization: Proc. Conf.
    • Dinic, E.A.1
  • 13
    • 84941865105 scopus 로고
    • Identification of critical paths in circuits with level-sensitive latches
    • Ann Arbor, MI, Tech. Rep. CSE-TR-160-93
    • T. Burks, K. Sakallah, and T. N. Mudge, “Identification of critical paths in circuits with level-sensitive latches,” Univ. Michigan, Ann Arbor, MI, Tech. Rep. CSE-TR-160-93, 1993.
    • (1993) Univ. Michigan
    • Burks, T.1    Sakallah, K.2    Mudge, T.N.3
  • 14
    • 72549090955 scopus 로고
    • Performance analysis and optimization of asynchronous circuits
    • California Inst. Technol., Caltech-CS-TR-91-01
    • S. Bums, “Performance analysis and optimization of asynchronous circuits,” Ph.D. dissertation, California Inst. Technol., Caltech-CS-TR-91-01, 1991.
    • (1991) Ph.D. dissertation
    • Bums, S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.