Idealized model for charged device electrostatic discharge

IEEE Transactions on Industry Applications

Volumn 35, Issue 1, 1999, Pages 240-258

  Greason, William D ^a  

^a UNIVERSITY OF WESTERN ONTARIO   (Canada)

Author keywords

Charged device model; Electrostatic discharge

Indexed keywords

EID: 0000557761     PISSN: 00939994     EISSN: None     Source Type: Journal    
DOI: 10.1109/28.740872     Document Type: Article

References (30)

1. W. D. Greason, "Electrostatic discharge: A charge driven phenomena," J. Electrostatics, vol. 28, no. 3, pp. 199-218, Sept. 1992.
2. Electrostatic Discharge in Electronics. New York: Wiley, 1992.
3. IEEE Guide on Electrostatic Discharge (ESD): Characterization of the ESD Environment. IEEE Std C62.47-1992.
4. D. L. Lin, "Effect of VLSI technology scaling on ESD current carrying capability," J. Electrostatics, vol. 39, no. 3, pp. 175-188, July 1997.
5. C. H. Diaz, T. E. Kopley, and P. J. Marcoux, "Building-in ESD/EOS reliability for sub-halfmicron CMOS processes," IEEE Trans. Electron Devices, vol. 43, pp. 991-999, June 1996.
6. D. L. Lin, "Electron multiplication and electrostatic discharge wave-forms," J. Appl. Phys.. vol. 71, pp. 2580-2586, Mar. 1992.
7. R. G. Renninger, "Mechanisms of charged-device electrostatic discharges," J. Electrostatics, vol. 28, pp. 253-283, Sept. 1992.
8. D. L. Lin and T. L. Welcher, "From lightning to charged-device model electrostatic discharge," J. Electrostatics, vol. 31, pp. 199-213, Dec. 1993.
9. H. M. Hyatt, "The resistive phase of an air discharge and the formation of fast risetime ESD pulses," J. Electrostatics, vol. 31, pp. 339-356, Dec. 1993.
10. D. Pommerenke, "ESD: Transient fields, arc simulation and rise time limit," J. Electrostatics, vol. 36, pp. 31-54, Nov. 1995.
11. R. Zaridze, D. Karkashadze, R. G. Djobava, D. Pommerenke, and M. Aidman, "Numerical calculation and measurement of transient fields from electrostatic discharges," IEEE Trans. Comp., Hybrids, Manufact. Technol. C. vol. 19, pp. 177-183, July 1996.
12. T. Wada, "ESD evaluation methods for a charged device model," IEEE Trans. Comp., Packag., Manufact. Technol. C, vol. 19, pp. 162-168, July 1996.
13. A. Wallash and M. Honda, "Field-induced breakdown ESD damage of magnetoresistive recording heads," in Proc. EOS/ESD Symp., EOS-19, Santa Clara, CA, Sept. 23-25, 1997, pp. 382-385.
14. A. J. Wallash, T. S. Hughbanks, and S. H. Voldman, "ESD failure mechanisms of inductive and magnetoresistive recording heads," J. Electrostatics, vol. 38, nos. 1-2, pp. 159-173, Oct. 1996.
15. W. D. Greason and S. Bulach, "Constant energy device test for electrostatic discharge (ESD) of semiconductor devices," IEEE Trans. Ind. Applicat.. vol. 33, pp. 286-297, Jan./Feb. 1997.
16. Standard for Electrostatic Discharge (ESD) Sensitivity Testing, Human Body Model (HBM)-Component Level, EOS/ESD-S5.1-1993.
17. Electrostatic Discharge Sensitivity Classification, Dep. Defense, Washington, DC, MIL-STD-883C, Notice 8, Method 3015.7, 1989.
18. Standard for Electrostatic Discharge (ESD) Sensitivity Testing, Machine Model (MM)-Component Level, ESD-S5.2-1994.
19. Draft Standard for Electrostatic Discharge (ESD) Sensitivity Testing, Charged Device Model (CDM) Non-Socketed Mode Component Level, EOS/ESD-DS5.3.1-1996.
20. W. R. Smythe, Static and Dynamic Electricity, 3rd ed. New York: McGraw-Hill, 1968.
21. A. Bouwers and P. G. Cath, "The maximum electric field strength for several simple electrode configurations," Philips Tech. Rev., vol. 6, no. 9, pp. 270-278, 1941.
22. D. K. Davies, "Charge generation on dielectric surfaces," J. Phys. D, Appl. Phys., vol. 2, pp. 1533-1537, 1969.
23. Y. L. Chow and M. M. Yovanovich, "The shape factor of the capacitance of a conductor," J. Appl. Phys., vol. 53, no. 12, pp. 8470-8475, 1982.
24. "The capacitances of two arbitrary conductors," J. Electrostatics., vol. 13, pp. 225-234, Aug. 1983.
25. L. R. Avery, "Charged device model testing: trying to duplicate reality," in Proc. EOS/ESD Symp., EOS-9, Orlando, FL, Sept. 29-Oct. 1, 1987, pp. 88-92.
26. K. Verhaege, G. Groeseneken, H. E. Maas, P. Egger, and H. Gieser, "Influence of tester, test method and device type on COM ESD testing," in Proc. EOS/ESD Symp., EOS-16, Las Vegas, NV, Sept. 27-29, 1994, pp. 49-62.
27. N. Khurana, T. Maloney, and W. Yeh, "ESD on CHMOS devices-equivalent circuits, physical models and failure mechanisms," in Proc. IEEE Reliability Physics Symp., Orlando, FL, Mar. 26-28, 1985, pp. 212-223.
28. T. J. Maloney, "Designing MOS inputs and outputs to avoid oxide failure in the charged device mode," in Proc. EOS/ESD Symp., EOS-10, Anaheim, CA, Sept. 27-29, 1988, pp. 220-227.
29. H. Pon, Kosonocky, and T. Maloney, "High current ESD damage to MOS I/O structures caused by charged video monitor surfaces and casings," in Proc. EOS/ESD Symp., EOS-11, New Orleans, LA, Sept. 26-28, 1989, pp. 78-83.
30. R. J. Smith and R. C. Dorf, Circuits, Devices, and Systems, 5th ed. New York: Wiley, 1992.