Low power logic design using push-pull pass-transistor logics

International Journal of Electronics

Volumn 84, Issue 5, 1998, Pages 467-478

  Paik, Woo Hyun ^a   Ki, Hoon Jae ^a   Kim, Soo Won ^a  

^a Korea University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0000512932     PISSN: 00207217     EISSN: 13623060     Source Type: Journal    
DOI: 10.1080/002072198134571     Document Type: Article

References (11)

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3. Chandrakasan, A. P., Sheng, S., and Broderson, R. W., 1992, Low-power CMOS digital design. IEEE Journal of Solid-state Circuits, 27, 473-484.
4. Guan, Z., and Almaini, E. A., 1995, One-bit adder design based on Reed-Muller expansions. International Journal of Electronics, 79, 519-529.
5. Guan, Z., Almaini, E. A., and Thomson, P., 1993, A simple and high speed CMOS carry chain adder architecture. International Journal of Electronics, 75, 743-752.
6. Hwang, K., 1979, Computer Arithmetic: Principles, Architecture, and Design (New York, U.S.A.: John Wiley &Sons).
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8. Ohkubo, N., Suzuki, M., Shinbo, T, Yamanaka, T, Shimizu, A., Sasaki, K., and Nakagome, Y, 1995, A 4.4ns CMOS 54 x 54-b multiplier using pass-transistor multiplexer. IEEE Journal of Solid-state Circuits, 30, 251-257.
9. Paik, W. H., Ki, H. J., and Kim, S. W., 1996, Push-pull pass-transistor logic family for low voltage and low power. 22nd European Solid-State Circuits Conference, pp. 116-119.
10. Parameswar, a., Hara, H., Sakurai, T, 1994, A high speed, low power, swing restored pass-transistor logic based multiply and accumulate circuit for multimedia applications. Custom Integrated Circuits Conference, pp. 278-281.
11. Yano, K., Yamanaka, T, NishiDa, T, Saito, M., Shimohigashi, K., and Shimizu, A., 1990, A 3.8-ns CMOS 16 x 16-b multiplier using complementary pass-transistor logic. IEEE Journal of Solid-state Circuits, 25, 388-394.