Providing deterministic delay guarantees in ATM networks

IEEE/ACM Transactions on Networking

Volumn 6, Issue 6, 1998, Pages 838-850

  Kweon, Seok Kyu ^b   Shin, Kang G ^a,b  

^a IEEE   (United States)

^b UNIVERSITY OF MICHIGAN   (United States)

Author keywords

ATM; Broadband ISDN; Cell multiplexing; Channel admissibility; Delay guarantee; Multimedia conferencing; Rate monotonic priority scheduling; Real time communication; Traffic controller

Indexed keywords

EID: 0000488125     PISSN: 10636692     EISSN: None     Source Type: Journal    
DOI: 10.1109/90.748093     Document Type: Article

References (29)

1. R. L. Cruz, "A calculus for network delay, part I: Network elements in isolation," IEEE Trans. Inform. Theory, vol. 37, pp. 114-131, Jan. 1991.
2. _, "A calculus for network delay, part II: Network analysis," IEEE Trans. Inform. Theory, vol. 37, pp. 132-142, Jan. 1991.
3. D. Ferrari and D. C. Verma, "A scheme for real-time channel establishment in wide-area networks," IEEE J. Select. Areas Commun., vol. 8, pp. 368-379, Apr. 1990.
4. H. Zhang and D. Ferrari, "Rate-controlled static-priority queueing," in Proc. IEEE INFOCOM'93, 1993, pp. 227-236.
5. H. Zhang and S. Keshav, "Comparison of rate-based service disciplines," in Proc. ACM SIGCOMM, 1991, pp. 113-121.
6. A. K. Parekh and R. G. Gallager, "A generalized processor sharing approach to flow control in integrated services networks: The single node case," IEEE/ACM Trans. Networking, vol. 1, pp. 344-357, June 1993.
7. C. Liu and J. W. Layland, "Scheduling algorithms for multiprogramming in a hard real-time environment," J. Assoc. Comput. Mach., vol. 20, no. 1, pp. 44-61, Jan. 1973.
8. D. D. Kandlur, K. G. Shin, and D. Ferrari, "Real-time communication in multi-hop networks," in Proc. 11th Int. Conf. Distributed Computing Systems, May 1991, pp. 300-307.
9. A. Demers, S. Keshav, and S. Shenker, "Analysis and simulation of a fair queueing algorithm," in Proc. ACM SIGCOMM, 1989, pp. 1-12.
10. A. K. Parekh and R. G. Gallager, "A generalized processor sharing approach to flow control in integrated services networks: The multiple node case," in Proc. IEEE INFOCOM'93, 1993, pp. 521-530.
11. E. Knightly, D. Wrege, J. Liebeherr, and H. Zhang, "Fundamental limits and tradeoffs of providing deterministic guarantees to VBR video traffic," in Proc. ACM SIGMETRICS, 1995, pp. 98-107.
12. D. Saha, S. Mukherjee, and S. K. Tripathi, "Multirate scheduling for guaranteed and predictive services in ATM networks," in Proc. IEEE RTSS, Dec. 1996, pp. 155-164.
13. D. E. Wrege, E. W. Knightly, H. Zhang, and J. Liebeherr, "Deterministic delay bounds for VBR video in packet-switching networks: Fundamental limits and practical trade-offs," IEEE/ACM Trans. Networking, vol. 4, pp. 352-362, June 1996.
14. M. de Prycker, Asynchronous Transfer Mode: Solution for Broadband ISDN. London, U.K.: Ellis Horwood, 1991.
15. D. D. Kandlur, K. G. Shin, and D. Ferrari, "Real-time communication in multi-hop networks," IEEE Trans. Parallel Distrib. Syst., vol. 5, pp. 1044-1056, Oct. 1994.
16. Q. Zheng, "Real-time fault-tolerant communication in computer network," Ph.D. dissertation, Dep. Elect. Eng. Comput. Sci., The University of Michigan, Ann Arbor, 1993.
17. H. Zhang, "Service disciplines for packet-switching integrated-services networks," Ph.D. dissertation, Dep. Comput. Sci., The University of California, Berkeley, 1993.
18. L. Georgiadis, R. Guérin, V. Peris, and K. N. Sivarajan, "Efficient network QoS provisioning based on per Node traffic shaping," in Proc. IEEE INFOCOM'96, 1996, pp. 102-110.
19. S. Kweon and K. G. Shin, "Traffic-controlled rate-monotonic priority scheduling," in Proc. IEEE INFOCOM'96, 1996, pp. 655-662.
20. D. Pickers and R. Fellman, "A VLSI priority packet queue with inheritance and overwrite," IEEE Trans. VLSI Syst., vol. 3, pp. 245-252, June 1995.
21. J. Chao, "A novel architecture for queue management in the ATM network," IEEE J. Select. Areas Commun., vol. 9, pp. 1110-1118, Sept. 1991.
22. H. J. Chao and N. Uzun, "A VLSI sequencer chip for ATM traffic shaper and queue management," IEEE J. Solid-State Circuits, vol. 27, pp. 1634-1643, Nov. 1992.
23. K. Toda, K. Nishida, E. Takahashi, N. Michell, and Y. Yamaguchi, "Design and implementation of a priority forwarding router chip for real-time interconnection networks," Int. J. Mini Microcomput., vol. 17, no. 1, pp. 42-51, 1995.
24. P. Lavoie and Y. Savaria, "A systolic architecture for fast stack sequential decoders," IEEE Trans. Commun., vol. 42, pp. 324-334, Feb./Mar./Apr. 1994.
25. C. Leiserson, "Systolic priority queues," in Proc. Caltech Conf. on VLSI, Jan. 1979, pp. 200-214.
26. S.-W. Moon, J. Rexford, and K. G. Shin, "Scalable hardware priority queue architectures for high-speed packet switches," in Proc. IEEE Real-Time Technology and Applications Symp., 1997, pp. 203-212.
27. H. J. Chao, "Architecture design for regulating and scheduling user's traffic in ATM networks," in Proc. ACM SIGCOMM, 1992, pp. 77-87.
28. S. J. Golestani, "A self-clocked fair queueing scheme for broadband applications," in Proc. IEEE INFOCOM'94, 1994, pp. 636-646.
29. J. Rexford, A. G. Greenberg, and F. Bonomi, "Hardware-efficient fair queueing architectures for high-speed networks," in Proc. IEEE INFOCOM'96, Mar. 1996, pp. 638-646.