Merged Arithmetic

IEEE Transactions on Computers

Volumn C-29, Issue 10, 1980, Pages 946-950

  Swartzlander, Earl E ^a  

^a TRW Defense and Space Systems Group ^*  (United States)

Author keywords

Complex multiplication computer arithmetic FFT butterfly operation inner product computation merged arithmetic multiplier adder signal processing arithmetic

Indexed keywords

EID: 0000479594     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.1980.1675482     Document Type: Article

References (12)

1. B. Gold and C. M. Rader, Digital Processing of Signals. New York: McGraw-Hill, 1969.
2. A. C. Salazar, Digital Signal Computers and Processors. New York: IEEE, 1977.
3. A. Peled and B. Liu, Digital Signal Processing. New York: Wiley, 1976.
4. A. V. Oppenheim and R. W. Shaffer, Digital Signal Processing. Englewood Cliffs, NJ: Prentice-Hall, 1975.
5. C. S. Wallace, “A suggestion for a fast multiplier,” IEEE Trans. Electron. Comput., Vol. EC-13, pp. 14-17, 1964.
6. L. Dadda, “Some schemes for parallel multipliers,” Alta Freq., Vol. 34, pp. 349-356, 1965.
7. W. J. Stenzel, W. J. Kubitz, and G. H. Garcia,'”A compact high-speed parallel multiplication scheme,” IEEE Trans. Comput., Vol. C-26, pp. 948-957, 1977.
8. L. Dadda, “On parallel digital multipliers’ Alta Freq., Vol. 45, pp. 574-580, 1976.
9. E. E. Swartzlander, Jr., B. K. Gilbert, and I. S. Reed, “Inner product computers,” IEEE Trans. Comput., Vol. C-27, pp. 21-31, 1978.
10. C. R. Baugh and B. A. Wooley, “A two's complement parallel array multiplication algorithm,” IEEE Trans. Comput., Vol. C-22, pp. 1045-1047, 1973.
11. A. Habibi and P. A. Wintz, “Fast multipliers,” IEEE Trans. Comput., Vol. C-19, pp. 153-157, 1970.
12. E. E. Swartzlander, Jr., “Merged arithmetic for signal processing,” in Proc. 4th IEEE Symp. Comput. Arithmetic, Santa Monica, CA, Oct. 1978, pp. 239–244.