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Volumn 34, Issue 9, 1999, Pages 1283-1289

The Mirrored Lateral SCR (MILSCR) as an ESD Protection Structure: Design and Optimization Using 2-D Device Simulation

Author keywords

Electrostatic discharge (ESD) protection; Silicon controlled rectifier (SCR); Two dimensional (2 D) device simulation

Indexed keywords


EID: 0000430988     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.782089     Document Type: Article
Times cited : (6)

References (9)
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  • 3
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    • Thermal breakdown of VLSI by ESD pulses
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    • (1990) Proc. Int. Reliability Physics Symp. , pp. 281-287
    • Lin, D.L.1
  • 4
    • 0014766404 scopus 로고
    • Avalanche injection and second breakdown in transistors
    • P. L. Hower and V. Gopala Krishna Reddi, "Avalanche injection and second breakdown in transistors," IEEE Trans. Electron Devices, vol. ED-17, no. 4, pp. 320-335, 1970.
    • (1970) IEEE Trans. Electron Devices , vol.ED-17 , Issue.4 , pp. 320-335
    • Hower, P.L.1    Gopala Krishna Reddi, V.2
  • 5
    • 0347351349 scopus 로고    scopus 로고
    • Device modeling: Limitations and perspectives for advanced technologies
    • Sept.
    • M. Rudan, M. Lorenzini, M. C. Vecchi, M. Valdinoci, and D. Ventura, "Device modeling: Limitations and perspectives for advanced technologies," in Proc. ESSDERC, Sept. 1998, pp. 25-32.
    • (1998) Proc. ESSDERC , pp. 25-32
    • Rudan, M.1    Lorenzini, M.2    Vecchi, M.C.3    Valdinoci, M.4    Ventura, D.5
  • 6
    • 0026839035 scopus 로고
    • A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI
    • Mar
    • C.-Y. Wu, M.-D. Ker, C.-Y. Lee, and J. Ko, "A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI," IEEE J. Solid-State Circuits, vol. 27, pp. 274-280, Mar 1992.
    • (1992) IEEE J. Solid-State Circuits , vol.27 , pp. 274-280
    • Wu, C.-Y.1    Ker, M.-D.2    Lee, C.-Y.3    Ko, J.4
  • 7
    • 0038185073 scopus 로고
    • The physics and modeling of latch-up in CMOS integrated circuits
    • Nov.
    • D. B. Estreich, "The physics and modeling of latch-up in CMOS integrated circuits," Tech. Rep. G-201-9, Nov. 1980.
    • (1980) Tech. Rep. G-201-9
    • Estreich, D.B.1
  • 9
    • 0025953251 scopus 로고
    • A low voltage triggering SCR for on-chip ESD protection at output and input pads
    • Jan.
    • A. Chatterjee, "A low voltage triggering SCR for on-chip ESD protection at output and input pads," IEEE Electron Device Lett., vol. 12, pp. 21-22, Jan. 1991.
    • (1991) IEEE Electron Device Lett. , vol.12 , pp. 21-22
    • Chatterjee, A.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.