메뉴 건너뛰기




Volumn 6, Issue 2, 1996, Pages 171-184

CMOS implementation of a voltage-mode fuzzy min-max controller

Author keywords

[No Author keywords available]

Indexed keywords


EID: 0000423430     PISSN: 02181266     EISSN: None     Source Type: Journal    
DOI: 10.1142/S0218126696000145     Document Type: Article
Times cited : (24)

References (19)
  • 2
    • 3042873722 scopus 로고
    • Low voltage current-mode and voltage-mode min and max circuit building blocks for analog CMOS fuzzy processors
    • Iizuka, Japan
    • J. R. Angulo and R. P. Loera, "Low voltage current-mode and voltage-mode min and max circuit building blocks for analog CMOS fuzzy processors", Proc. 3rd Int. Conf. on Fuzzy Logic, Neural Networks and Soft Computing, Iizuka, Japan, 1994.
    • (1994) Proc. 3rd Int. Conf. on Fuzzy Logic, Neural Networks and Soft Computing
    • Angulo, J.R.1    Loera, R.P.2
  • 3
    • 0027592645 scopus 로고
    • A fuzzy inference engine in nonlinear analog mode and its application to a fuzzy logic control
    • T. Yamakawa, "A fuzzy inference engine in nonlinear analog mode and its application to a fuzzy logic control", IEEE Trans. Neural Networks 4 (1993) 496-522.
    • (1993) IEEE Trans. Neural Networks , vol.4 , pp. 496-522
    • Yamakawa, T.1
  • 4
    • 0028400634 scopus 로고
    • A Gaussian synapse circuit for analog VLSI neural networks
    • J. Choi, B. J. Sheu, and J. C.-F. Chang, "A Gaussian synapse circuit for analog VLSI neural networks", IEEE Trans. VLSI Sys. 2 (1994) 129-133.
    • (1994) IEEE Trans. VLSI Sys. , vol.2 , pp. 129-133
    • Choi, J.1    Sheu, B.J.2    Chang, J.C.-F.3
  • 8
    • 0041737937 scopus 로고
    • Current mode analog fuzzy hardware with voltage input interface and normalization locked loop
    • M. Sasaki, N. Ishikawa, F. Ueno, and T. Inoue, "Current mode analog fuzzy hardware with voltage input interface and normalization locked loop", IEICE Trans. Fundamentals E57-A (1992) 650-654.
    • (1992) IEICE Trans. Fundamentals , vol.E57-A , pp. 650-654
    • Sasaki, M.1    Ishikawa, N.2    Ueno, F.3    Inoue, T.4
  • 10
    • 0027542561 scopus 로고
    • Fuzzy min-max neural networks - Part 2: Clustering
    • P. K. Simpson, "Fuzzy min-max neural networks - Part 2: Clustering", IEEE Trans. Fuzzy Sys. 1 (1993) 32-45.
    • (1993) IEEE Trans. Fuzzy Sys. , vol.1 , pp. 32-45
    • Simpson, P.K.1
  • 11
    • 0027649305 scopus 로고
    • A fuzzy neural network model and its hardware implementation
    • Y.-H. Kuo, C.-I Kao, and J.-J. Chen, "A fuzzy neural network model and its hardware implementation", IEEE Trans. Fuzzy Sys. 1 (1993) 171-183.
    • (1993) IEEE Trans. Fuzzy Sys. , vol.1 , pp. 171-183
    • Kuo, Y.-H.1    Kao, C.-I.2    Chen, J.-J.3
  • 16
    • 0028438876 scopus 로고
    • A VLSI fuzzy inference processor based on a discrete analog approach
    • V. Catania, A. Puliafito, M. Russo, and L. Vita, "A VLSI fuzzy inference processor based on a discrete analog approach", IEEE Trans. Fuzzy Sys. 2 (1994) 93-106.
    • (1994) IEEE Trans. Fuzzy Sys. , vol.2 , pp. 93-106
    • Catania, V.1    Puliafito, A.2    Russo, M.3    Vita, L.4
  • 17
    • 0027678964 scopus 로고
    • Computing centroids in current-mode technique
    • M. Tartagni and P. Perona, "Computing centroids in current-mode technique", Electronics Lett. 29 (1993) 1811-1813.
    • (1993) Electronics Lett. , vol.29 , pp. 1811-1813
    • Tartagni, M.1    Perona, P.2
  • 18
    • 0025448088 scopus 로고
    • Fuzzy multiple-input maximum and minimum circuits in current mode and their analysis using bounded difference equations
    • M. Sasaki, T. Inoue, Y. Shirai, and F. Ueno, "Fuzzy multiple-input maximum and minimum circuits in current mode and their analysis using bounded difference equations", IEEE Trans. on Com. 39 (1990) 764-774.
    • (1990) IEEE Trans. on Com. , vol.39 , pp. 764-774
    • Sasaki, M.1    Inoue, T.2    Shirai, Y.3    Ueno, F.4
  • 19
    • 3042881615 scopus 로고
    • A design of current-mode analog circuits for fuzzy inference hardware systems
    • K. Tsukano, T. Inoue, and F. Ueno, "A design of current-mode analog circuits for fuzzy inference hardware systems", Proc. ISCAS (1993) 1358-1388.
    • (1993) Proc. ISCAS , pp. 1358-1388
    • Tsukano, K.1    Inoue, T.2    Ueno, F.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.