Junction Termination Extension for Near-Ideal Breakdown Voltage in p-n Junctions

IEEE Transactions on Electron Devices

Volumn 33, Issue 10, 1986, Pages 1601-1608

  Temple, Victor A K ^a   Tantraporn, W ^a  

^a GENERAL ELECTRIC COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0000393662     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1986.22713     Document Type: Article

References (7)

1. V. A. K. Temple and M. S. Adler, “The theory and application of a simple etch contour for near ideal breakdown in plane and planar p-n junction,” IEEE Trans. Electron Devices, vol. ED-23, pp. 950-955, 1976.
2. V. A. K. Temple, “Practical aspects of the depletion etch method in high-voltage devices,” IEEE Trans. Electron Devices, vol. ED-27, pp. 977–982, 1980.
3. V. A. K. Temple and M. S. Adler, “A substrate etch geometry for near ideal breakdown voltage in p-n junction devices,” IEEE Trans. Electron Devices, vol. ED-24, pp. 1077–1081, 1977.
4. V. A. K. Temple, “JTE, a new technique for increasing breakdown voltage and controlling surface fields,” in IEDM Tech. Dig., p. 432, 1977.
5. —, “Increased avalanche breakdown voltage and controlled surface fields with JTE,” IEEE Trans. Electron Devices, vol. ED-30, p. 954, 1983.
6. M. S. Adler and V. A. K. Temple, “Theory and breakdown voltage of planar junctions with a single field limiting ring,” IEEE Trans. Electron Devices, vol. ED-24, p. 107, 1977.
7. M. S. Adler V. A. K. Temple, and R. C. Rustay, General Electric Rep. 81CRD190, 1981.