A capacity allocation problem with integer side constraints

European Journal of Operational Research

Volumn 109, Issue 1, 1998, Pages 170-182

  Beril Toktay, L ^a   Uzsoy, Reha ^a  

^a SCHOOL OF INDUSTRIAL ENGINEERING   (United States)

Author keywords

Network flows; Scheduling; Semiconductor manufacturing

Indexed keywords

EID: 0000262471     PISSN: 03772217     EISSN: None     Source Type: Journal    
DOI: 10.1016/s0377-2217(98)80011-8     Document Type: Article

References (14)

1. Aboudi, R., Hallefjord, A., and Jornsten, K. (1991), "A facet generation and relaxation technique applied to an assignment problem with side constraints", European Journal of Operational Research, 50, 335-344.
2. Ahuja, R.K., Magnanti, T.L., and Orlin, J.B. (1993), Network Flows: Theory, Algorithms and Applications, Prentice-Hall, Englewood Cliffs, NJ.
3. Bai, X., Srivatsan, N., and Gershwin, S.B. (1990), "Hierarchical real-time scheduling of a semiconductor fabrication facility", in: Proceedings of the Ninth IEEE International Electronics Manufacturing Technology Symposium, Washington, DC, October 1990.
4. CPLEX Optimization, Inc. (1993), "Using the CPLEX Callable Library and CPLEX Mixed Integer Library".
5. Elleby, P., Fargher, H.E., and Addis, T.R. (1989), "A constraint based scheduling system for VLSI wafer fabrication", in: J. Browne, (ed.,) Knowledge-Based Production Management Systems, Elsevier Science Publishers, Amsterdam.
6. Glassey, C.R., and Resende, M.G.C. (1988), "Closed-loop job release control for VLSI circuit manufacturing", IEEE Transactions on Semiconductor Manufacturing 1, 36-46.
7. Graves, S.C., Meal, H.C., Stefek, D., and Zeghmi, A.H. (1983), "Scheduling of re-entrant flow shops", Journal of Operations Management 3, 197-207.
8. Kempf, K.G. (1994), "Intelligently scheduling semiconductor wafer fabrication", in: M. Zweben and M. Fox (eds.), Intelligent Scheduling Systems, Morgan Kaufmann, Los Altos, CA.
9. Lu, S.H., Ramaswamy, D., and Kumar, P.R. (1994), "Efficient scheduling policies to reduce mean and variance of cycle time in semiconductor manufacturing plants", IEEE Transactions on Semiconductor Manufacturing 7, 374-388.
10. Minoux, M. (1989), "Network synthesis and optimum network design problems: Models, solution methods and applications", Networks 19, 313-360.
11. Runyan, W.R., and Bean, K.E. (1990), Semiconductor Integrated Circuit Processing Technology, Addison-Wesley, Reading, MA.
12. Uzsoy, R., Lee, C.Y., and Martin-Vega, L.A. (1992), "A review of production planning and scheduling models in the semicon-ductor industry - Part I: System characteristics, performance evaluation and production planning", IIE Transactions on Scheduling and Logistics 4, 47-60.
13. Uzsoy, R., Lee, C.Y., and Martin-Vega, L.A. (1994), "A review of production planning and scheduling models in the semiconductor industry - Part II: Shop-floor control", IIE Transactions on Scheduling and Logistics 26, 44-55.
14. Wein, L.M. (1988), "Scheduling semiconductor wafer fabrication", IEEE Transactions on Semiconductor Manufacturing 1, 115-129.