Characterization and Suppression of Drain Coupling in Submicrometer EPROM Cells

IEEE Transactions on Electron Devices

Volumn 34, Issue 12, 1987, Pages 2463-2468

  Prall, Kirk ^a   Kinney, Wayne I ^a   Macro, Jon ^a  

^a Signetics Corporation ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0000240970     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1987.23336     Document Type: Article

References (14)

1. B. Eitan and D. Frohman-Bentchkowsky, “Surface conduction in short-channel MOS devices as a limitation to VLSI scaling,” IEEE Trans. Electron Devices, vol. ED-29, p. 254, 1982.
2. M. Wada, S. Mimura, and H. Iizuka, “Limiting factors for prognm-ming EPROM of reduced dimensions,” in IEDM Tech. Dig., pp. 38-41, 1980.
3. Y. Nishi and H. Iizuka, “Nonvolatile memories,” in Applied Solid State Science, Supplement 2A. New York: Academic, 1981.
4. E. Nicollian and J. Brews, MOS Physics and Technology. New York: Wiley Interscience, 1982, pp. 77-84.
5. R. Shrivastava and K. Fitzpatrick, “A simple model for the overlap capacitance of a VLSI MOS device,” IEEE Trans. Electron Devices, vol. ED-29, no. 12, pp. 1870-1875, Dec. 1982.
6. B. J. Sheu and P. K. Ko, “An analytical model for intrinsic capac-tances of short-channel MOSFET's,” in IEDM Tech. Dig., pp. SCO-SOS, 1984.
7. P. K. Chatterjee, P. Yang, and H. Shichijo, “Modelling of small MOS devices and device limits,” IEE Proc., vol. 130, pt. I, no. 3, pp. 105-126, June 1983.
8. S. Selberherr, A. Schutz, and H. Potzl, “MINIMOS-A two-dimensional MOS transistor analyzer,” IEEE Trans. Electron Devices, vol. ED-27, no. 8, Aug. 1980.
9. K. Komori et al., “A high performance memory cell technology “or megabit EPROMs,” in IEDM Tech. Dig., pp. 627-630, 1985.
10. S. Ohya, M. Kikuchi, and Y. Narita, “Single 5V EPROM with submicron memory transistor and OnChip high voltage generator,” in IEDM Tech. Dig., pp. 570-573, 1983.
11. Wafer Scale Integration Patent.
12. Y. Mizutani and K. Makita, “A new EPROM cell with a sidewall floating gate for high-density and high-performance device,” in IEDM Tech. Dig., pp. 635-638, 1985.
13. M. Van Buskirk et al., “EPROM's graduate to 256K'density with scaled N-channel process,” Electronics, Feb. 24, 1983.
14. P. K. Chatterjee, W. R. Hunter, T. C. Holloway, and Y. T. Lin, “The impact of scaling laws on the choice of n-channel or p-chanrel for MOS VLSI,” IEEE Electron Device Lett., vol. EDL-1, no. 10, Oct. 1980.