-
1
-
-
0027557033
-
Finite precision error analysis of neural network hardware implementations
-
Mar.
-
J. L. Holt and J. N. Hwang, "Finite precision error analysis of neural network hardware implementations," IEEE Trans. Comput., vol. 42, pp. 281-290, Mar. 1993.
-
(1993)
IEEE Trans. Comput.
, vol.42
, pp. 281-290
-
-
Holt, J.L.1
Hwang, J.N.2
-
2
-
-
0027878015
-
Machine and bit precision influrence on the Hopfield-Tank model for the TSP
-
Japan, Oct.
-
W. Lin, J. G. Delgado-Frias, S. Vassiliadis, and G. G. Pechanek, "Machine and bit precision influrence on the Hopfield-Tank model for the TSP," in Proc. Int. Joint Conf. Neural Networks, Japan, Oct. 1993.
-
(1993)
Proc. Int. Joint Conf. Neural Networks
-
-
Lin, W.1
Delgado-Frias, J.G.2
Vassiliadis, S.3
Pechanek, G.G.4
-
3
-
-
0026896088
-
Digital implementation methods for nonlinear functions in neural networks
-
to be published
-
H. K. Kwan, "Digital implementation methods for nonlinear functions in neural networks," IEEE Trans. Neural Networks, to be published.
-
IEEE Trans. Neural Networks
-
-
Kwan, H.K.1
-
4
-
-
0000144709
-
Implementation issues of sigmoid function and its derivative for VLSI digital neural networks
-
May
-
A. Murtagh and A. C. Tsoi, "Implementation issues of sigmoid function and its derivative for VLSI digital neural networks," in Proc. Inst. Elect. Eng., vol. 139, Pt. E, May 1992, pp. 207-214.
-
(1992)
Proc. Inst. Elect. Eng.
, vol.139
, Issue.PART E
, pp. 207-214
-
-
Murtagh, A.1
Tsoi, A.C.2
-
5
-
-
0026397798
-
Simple approximation of sigmoid functions: Realistic design of digital VLSI neural networks
-
C. Alippi and G. Storti-Gajani, "Simple approximation of sigmoid functions: Realistic design of digital VLSI neural networks," in Int. Symp. Circuits Syst., 1991, pp. 1505-1508.
-
(1991)
Int. Symp. Circuits Syst.
, pp. 1505-1508
-
-
Alippi, C.1
Storti-Gajani, G.2
-
6
-
-
0024766094
-
Efficient implementation of piecewise linear activation function for digital VLSI neural networks
-
Nov.
-
D. J. Myers and G. Storti-Gajani, "Efficient implementation of piecewise linear activation function for digital VLSI neural networks," Electron. Lett., vol. 25, no. 24, pp. 1662-1663, Nov. 1989.
-
(1989)
Electron. Lett.
, vol.25
, Issue.24
, pp. 1662-1663
-
-
Myers, D.J.1
Storti-Gajani, G.2
-
7
-
-
0026898265
-
Alternating minimization and Boltzmann machine learning
-
July
-
W. Byrne, "Alternating minimization and Boltzmann machine learning," IEEE Trans. Neural Networks, vol. 3, pp. 612-620, July 1992.
-
(1992)
IEEE Trans. Neural Networks
, vol.3
, pp. 612-620
-
-
Byrne, W.1
-
8
-
-
0016542594
-
Multiplication using logarithms implemented with read-only memory
-
Aug.
-
T. A. Brubaker and J. C. Becker, "Multiplication using logarithms implemented with read-only memory," IEEE Trans. Comput., vol. 24, Aug. 1975.
-
(1975)
IEEE Trans. Comput.
, vol.24
-
-
Brubaker, T.A.1
Becker, J.C.2
-
9
-
-
0024888743
-
VLSI architectures for neural networks
-
Dec.
-
P. Treleaven, M. Pacheco, and M. Vellasco, "VLSI architectures for neural networks," IEEE Micro., pp. 8-27, Dec. 1989.
-
(1989)
IEEE Micro.
, pp. 8-27
-
-
Treleaven, P.1
Pacheco, M.2
Vellasco, M.3
-
10
-
-
33747633649
-
Neural networks on silicon
-
M. Sami and F. Distante, Eds. Amsterdam, The Netherlands: Elsevier
-
P. Treleaven and M. Vellasco, "Neural networks on silicon," in Wafer Scale Integration, III, M. Sami and F. Distante, Eds. Amsterdam, The Netherlands: Elsevier, 1990.
-
(1990)
Wafer Scale Integration, III
-
-
Treleaven, P.1
Vellasco, M.2
-
11
-
-
33747661967
-
-
IBM Endicott, NY, IBM Tech. Rep. TR 01.C492, Dec.
-
M. Zhang, J. G. Delgado-Frias, S. Vassiliadis, and G. G. Pechanek, "Hardwired sigmoid generator," IBM Endicott, NY, IBM Tech. Rep. TR 01.C492, Dec. 1992.
-
(1992)
Hardwired Sigmoid Generator
-
-
Zhang, M.1
Delgado-Frias, J.G.2
Vassiliadis, S.3
Pechanek, G.G.4
-
12
-
-
0024682692
-
Table-driven implementation of the exponential function for IEEE floating-point arithmetic
-
June
-
P. T. Tang, "Table-driven implementation of the exponential function for IEEE floating-point arithmetic," ACM Trans. Math. Software, vol. 15, no. 2, pp. 144-157, June 1989.
-
(1989)
ACM Trans. Math. Software
, vol.15
, Issue.2
, pp. 144-157
-
-
Tang, P.T.1
-
13
-
-
0026115342
-
An accurate elementary mathematical library for the IEEE floating point standard
-
March
-
S. Gal and B. Bachelis, "An accurate elementary mathematical library for the IEEE floating point standard," ACM Trans. Math. Software, vol. 17, no. 1, pp. 26-45, March 1991.
-
(1991)
ACM Trans. Math. Software
, vol.17
, Issue.1
, pp. 26-45
-
-
Gal, S.1
Bachelis, B.2
-
14
-
-
0001527561
-
Automatic computations of exp, log, ratios and square
-
July
-
T. C. Chen, "Automatic computations of exp, log, ratios and square," IBM J. Res. Dev., p. 380, July 1972.
-
(1972)
IBM J. Res. Dev.
, pp. 380
-
-
Chen, T.C.1
-
15
-
-
0024719230
-
AS/370 sign-magnitude floating point adder
-
Aug.
-
S. Vassiliadis, D. S. Lemon, and M. Putrino, "AS/370 sign-magnitude floating point adder," IEEE J. Solid-State Circuits, vol. 24, pp. 1062-1070, Aug. 1989.
-
(1989)
IEEE J. Solid-State Circuits
, vol.24
, pp. 1062-1070
-
-
Vassiliadis, S.1
Lemon, D.S.2
Putrino, M.3
-
16
-
-
0025532312
-
A VLSI architecture for high-performance, low-cost, on-chip learning
-
June
-
D. Hammerstrom, "A VLSI architecture for high-performance, low-cost, on-chip learning," in IEEE Int. Joint Conf. Neural Networks, vol. II, June 1990, pp. 537-544.
-
(1990)
IEEE Int. Joint Conf. Neural Networks
, vol.2
, pp. 537-544
-
-
Hammerstrom, D.1
-
17
-
-
0025213664
-
WSI architecture of a neurocomputer module
-
U. Ramacher, M. Wesseling, and K. Goser, "WSI architecture of a neurocomputer module," in IEEE Int. Conf. Wafer Scale Integration, 1990, pp. 124-130.
-
(1990)
IEEE Int. Conf. Wafer Scale Integration
, pp. 124-130
-
-
Ramacher, U.1
Wesseling, M.2
Goser, K.3
-
18
-
-
0043028364
-
A VLSI systolic array dedicated to Hopfield neural network
-
J. Delgado-Frias and W. Moore, Eds. Boston, MA: Kluwer
-
F. Blayo and P. Hurat, "A VLSI systolic array dedicated to Hopfield neural network," in VLSI Artificial Intell., J. Delgado-Frias and W. Moore, Eds. Boston, MA: Kluwer, 1989, pp. 255-264.
-
(1989)
VLSI Artificial Intell.
, pp. 255-264
-
-
Blayo, F.1
Hurat, P.2
-
19
-
-
33747675100
-
SPIN: A sequential pipelined neurocomputer
-
San Jose, CA, Nov.
-
S. Vassiliadis, G. Pechanek, and J. Delgado-Frias, "SPIN: A sequential pipelined neurocomputer," in Proc. IEEE Int. Conf. Tools Artificial Intell., San Jose, CA, Nov. 1991.
-
(1991)
Proc. IEEE Int. Conf. Tools Artificial Intell.
-
-
Vassiliadis, S.1
Pechanek, G.2
Delgado-Frias, J.3
-
20
-
-
0026954181
-
Digital neural emulators using tree accumulation and communication structures
-
Nov.
-
G. G. Pechanek, S. Vassiliadis, and J. G. Delgado-Frias, "Digital neural emulators using tree accumulation and communication structures," IEEE Trans. Neural Networks, vol. 3, pp. 934-950, Nov. 1992.
-
(1992)
IEEE Trans. Neural Networks
, vol.3
, pp. 934-950
-
-
Pechanek, G.G.1
Vassiliadis, S.2
Delgado-Frias, J.G.3
-
21
-
-
0041128413
-
A VLSI pipelined neuroemulator
-
J. Delgado-Frias and W. Moore, Eds. New York: Plenum
-
J. G. Delgado-Frias, S. Vassiliadis, G. G. Pechanek, W. Lin, S. Barber, and H. Ding, "A VLSI pipelined neuroemulator," in VLSI for Neural Networks and Artificial Intelligence, J. Delgado-Frias and W. Moore, Eds. New York: Plenum, 1993.
-
(1993)
VLSI for Neural Networks and Artificial Intelligence
-
-
Delgado-Frias, J.G.1
Vassiliadis, S.2
Pechanek, G.G.3
Lin, W.4
Barber, S.5
Ding, H.6
-
23
-
-
33747693411
-
-
IBM, Austin, TX, IBM Tech. Rep. TR 51.0802, Dec.
-
S. Vassiliadis, M. Zhang, and J. G. Delgado-Frias, "Elementary function generators for neural network emulators," IBM, Austin, TX, IBM Tech. Rep. TR 51.0802, Dec. 1993.
-
(1993)
Elementary Function Generators for Neural Network Emulators
-
-
Vassiliadis, S.1
Zhang, M.2
Delgado-Frias, J.G.3
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